1. Field of the Invention
The invention relates to an analog to digital converter, and more particularly to an analog to digital converter reducing the effects of charge injection, clock feedthrough and voltage sampling errors.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional (N+M)-bit analog to digital converter. A reference voltage generating circuit 12 generates a plurality of first reference voltages 102 and a plurality of second reference voltages 101 between the voltages VRT and VRB. A most significant bit (MSB) comparator 15 receives and compares the first reference voltage 102 with the input voltage Vin. Two least most significant (LSB) comparators 11 and 13 receive and compare the second reference voltage 101 with the input voltage Vin. The reference voltage generating circuit 12 generates (2N−1) first reference voltages 102 between voltage VRT and VRB, and then generates (2M−1) second reference voltages 101 between two adjacent first reference voltages.
After the input voltage Vin is compared by the MSB comparator 15, a first thermometer code 105 is generated and transmitted to an MSB data encoder 17 to acquire N-bit digital code 108. The digital code 108 is transmitted and temporarily stored in MSB data latch 18.
When the input voltage Vin has been compared by the MSB comparator 15 based on the first reference voltages 102, it can be determined where in the range between the two first reference voltages the input voltage falls. The input voltage Vin is then compared with the second reference voltages by LSB comparators 11 and 13 to generate second thermometer codes 103 and 104. LSB data encoder 14 generates and transmits an M-bit digital code 106 to LSB data selector and latch 19 based on the second thermometer code 103. A LSB data encoder 16 generates and transmits an M-bit digital code 107 to LSB data selector and latch 19 based on the second thermometer code 104.
Because the N-bit digital code generated by MSB data encoder 17 is one clock cycle faster than the M-bit digital code generated by LSB encoder 14 or 16, the MSB data latch 18 transmits the N-bit digital code to the adder 19 after a delay of one clock cycle to combine with the M-bit digital code to acquire an (N+M)-bit digital data of the input voltage Vin.
If the frequency of the MSB comparator 15 is Fs, the frequency of LSB comparators 11 and 13 is ½FS. Since the sampling circuits for MSB comparator 15, and LSB comparators 11 and 13 are different, a sampling error is generated. This causes the voltage sampled by the MSB comparator 15, LSB comparators 11 and 13 to be different, thus, the accuracy of analog-to-digital conversion suffers.
Moreover, the MSB comparator 15, LSB comparators 11 and 13, employ single-ended amplifiers which easily generate charge injection and clock feedthrough when the switches of the comparators are switched.